Paolo Ienne
![photo placeholder image](/private/common/photos/links/101954.jpg?ts=1725164673)
Full Professor
Secretariat
Chantal SchneebergerStation 14
CH-1015 Lausanne
Tel. 41 21 693 26 41
chantal.schneeberger@epfl.ch
EPFL IC IINFCOM LAP
INF 137 (Bâtiment INF)
Station 14
1015 Lausanne
+41 21 693 26 25
+41 21 693 26 41
Office:
INF 137
EPFL
>
IC
>
IINFCOM
>
LAP
Web site: Web site: https://lap.epfl.ch/
Fields of expertise
Biography
Paolo Ienne has been a Professor at the EPFL since 2000 and heads the Processor Architecture Laboratory (LAP). Prior to that, he worked for the Semiconductors Group of Siemens AG, Munich, Germany (which later became Infineon Technologies AG) where he was at the head of the Embedded Memories unit in the Design Libraries division. His research interests include various aspects of computer and processor architecture, FPGAs and reconfigurable computing, electronic design automation, and computer arithmetic. Ienne was a recipient of Best Paper Awards at the 20th, 24th, and 28th ACM/SIGDA International Symposia on Field-Programmable Gate Arrays (FPGA), in 2012, 2016, and 2020, at the 19th, 30th, and 31st International Conference on Field-Programmable Logic and Applications (FPL), in 2009, 2020, and 2021, at the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), in 2007, and at the 40th Design Automation Conference (DAC), in 2003; many other papers have been candidates to Best Paper Awards in prestigious venues. He has served as general, programme, and topic chair of renown international conferences, including organizing in Lausanne the 26th International Conference on Field-Programmable Logic and Applications (FPL) in 2016. He serves on the steering committee of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) and of the IEEE Symposium on Computer Arithmetic (ARITH), and chairs the steering committee of the International Conference on Field-Programmable Logic and Applications (FPL). Ienne has guest edited a number of special issues and special sections on various topics for IEEE and ACM journals. He is regularly member of program committees of international workshops and conferences in the areas of design automation, computer architecture, embedded systems, compilers, FPGAs, and asynchronous design. He has been an associate editor of ACM Transactions on Architecture and Code Optimization (TACO), since 2015, of ACM Computing Surveys (CSUR), since 2014, and of ACM Transactions on Design Automation of Electronic Systems (TODAES), from 2011 to 2016.Publications
Other publications
Teaching & PhD
Teaching
Computer Science
Communication Systems